1. Field of the Invention
The present invention relates to an electrode-wiring substrate and a display device. For example, the electrode-wiring substrate may be a TFT (Thin Film Transistor) substrate and the display device may be a liquid crystal display device.
2. Description of the Related Art
Lately, in the field of display devices, which are man-machine interfaces, conventionally used cathode-ray tube (CRT) displays are being replaced with flat panel displays having the advantages of being thin, space-saving, lightweight and power-thrifty. In particular, it is no exaggeration to state that the flat panel display is applied to every monitor for mobile applications such as digital cameras, cellular phones and PDAs (Personal Digital Assistances).
There are three major flat panel displays for the above-mentioned applications: FEDs (Field Emission Displays); LCDs (Liquid Crystal Displays); and EL (Electroluminescence) displays. For each of the three displays, there are active displays including a drive TFT in each pixel and passive displays including no drive element. However, in Japan, the active displays are the favored ones in terms of superior image quality.
The flat panel displays for mobile applications as described above are spreading remarkably. Recently, on the market, there is a tendency to increase the size of a display screen and decrease the size of a peripheral region of the panel. That is, it has been required to equalize the outside shape of the panel and the effective size of the screen as possible. Due to demand for high-resolution, it has also been required to provide a plurality of electrode wires.
Further, in the field of flat panel displays, especially displays for cellular phones, it has also been required on the market in recent years to position the display screen at the center of the outside shape. However, in general, gate electrode terminals and source electrode terminals are formed in the peripheral region at one of the four sides of the screen, respectively. Thus, terminal regions are provided at two of the four sides of the screen. If the terminal regions are provided at the two sides of the screen, the center of the display screen is shifted to the left or right. Therefore, without taking the peripheral regions at the left and right sides of the display screen, the gate electrode terminals and the source electrode terminals are arranged only in one of the peripheral regions at the top or bottom sides of the display screen, thereby positioning the screen at the center.
On the other hand, in order to provide a display device of high manufacturing yield in which a number of electrode wires are connected to signal input terminals formed in the peripheral region at one of the sides of the display screen, the peripheral region needs to have a certain size. Therefore, what is important is to reduce the size of the peripheral region. However, if the region for forming the electrode wires is reduced, the pitch between the wires is also reduced. This may lead to a problem of a decrease in yield. In particular, as to COG (Chip On Glass) devices, a decrease in chip size for cost reduction requires further reduction of the pitch between the wires in a mounting region, thereby decreasing the yield to a further extent. In driver monolithic displays in which drivers are formed in the peripheral region, such a problem does not arise because the terminals are not concentrated at one of the sides of the display screen.
Japanese Patent No. 3276557 discloses a liquid crystal display device as a solution to this problem. The display device of Japanese Patent No. 3276557 includes multilayer wires of two or more layers prepared by connecting part of a conductive wire to another conductive wire via a contact hole such that the conductive wires overlap each other with an interlayer insulating film interposed therebetween. More specifically, as conductive wires for connecting gate electrode wires to gate electrode terminals, common first conductive wires made of gate material are formed and then second conductive wires made of source material are formed on the first conductive wires with an interlayer insulating layer interposed therebetween to obtain two-layered conductive wires. Further, contact holes are opened so that the gate electrode wires, gate electrode terminals and second conductive wires are electrically connected. In this way, the first and second conductive wires are connected.
Referring to FIGS. 7, 8 and 9, the liquid crystal display device of Japanese Patent No. 3276557 is described in further detail. FIG. 7 is a plan view illustrating part of the conductive wires disclosed by Japanese Patent No. 3276557, FIG. 8 is a sectional view taken along the line A-B shown in FIG. 7 and FIG. 9 is a sectional view illustrating a conductive wiring connecting part.
FIG. 7 shows a display region 201, gate (scanning electrode) terminals 202, source (signal electrode) terminals 203, conductive wire connecting parts 204, gate electrode wires 205 and source electrode wires 206. FIG. 8 shows a glass substrate 207, gate connection wires 208, an interlayer insulating layer 209 and source connection wires 210. The gate connection wires 208 and source connection wires 210 provide a two-layered structure with the interlayer insulating layer 209 interposed therebetween. The gate connection wires 208 are patterned simultaneously when the gate electrode wires 205 are patterned in the process of forming the gate wires on a TFT (Thin Film Transistor) array substrate. The source connection wires 210 are patterned simultaneously when the source electrode wires 206 are patterned in the process of forming the source wires on the TFT array substrate.
In FIG. 9, reference numeral 211 indicates a contact hole (conductive wire connecting part 204 ). By providing the contact hole 211, the gate connection wire 208 and the source connection wire 210 are arranged to coincide with each other. Therefore, two conductive wires are arranged in space for a single conductive wire. In this case, in a region for forming routing wires which connect the gate electrode wires to the gate terminals, the source connection wires 210 are stacked on the gate connection wires 208 with the interlayer insulating layer 209 interposed therebetween. Therefore, as compared with a common arrangement of the gate connection wires only, the routing wire region (corresponding to the peripheral region) is reduced down to about ½. That is, the peripheral region is significantly reduced in size.
Recently, reflective liquid crystal display devices and transmittive liquid crystal display devices which allow display in both reflective and transmissive modes are becoming the mainstream of monitors for the above-described mobile applications. In particular, the transmittive liquid crystal display devices which allow display in both reflective and transmissive modes have features of the reflective mode such as improved display recognition under bright ambient light and features of the transmissive mode such as improved display recognition under dark ambient light. Regardless of the degree of brightness of the ambient light, clear display is achieved. Therefore, such display devices are most required ones on the market. For example, a liquid crystal display panel disclosed by Japanese Patent No. 3377447 is an example of the transmittive liquid crystal display devices. In this liquid crystal display device, a first conductive layer (transparent conductive film) of high light transmittance and a second conductive layer (reflective conductive film) of high light reflectance, which are electrically connected to each other, are formed in a single pixel region to provide a pixel electrode. The first and second conductive layers are formed at different levels with an insulating layer made of an organic resin interposed therebetween.
The liquid crystal display device of Japanese Patent No. 3276557 includes the routing wires provided by stacking the source connection wires 210 immediately above the gate connection wires 208 with the interlayer insulating layer 209 interposed therebetween. This structure brings about the following three problems of manufacturing yield. First, since the interlayer insulating layer 209 are sandwiched between the conductive wires 208 and 210, display quality may presumably deteriorate due to the effect of the capacitance of the interlayer insulating layer 209 sandwiched between the gate and source conductive wires 208 and 210 (hereinafter may be referred to capacitance interaction). For example, due to the capacitance of the interlayer insulating layer 209, signal transmission delay occurs to deteriorate display quality. Further, an increase in impedance leads to an increase in power consumption, which is a critical defect in terms of mobile applications.
Second, electrostatic breakdown may possibly occur in the interlayer insulating layer 209. Wires where the electrostatic breakdown has occurred bring about defects in gate electrode wires in the display region, resulting in reduction in yield.
Third, parts of the obtained substrate where the gate connection wire 208, interlayer insulating layer 209 and source connection wire 210 are stacked give a large difference in height from parts of the interlayer insulating layer 209 (interlayer insulating layer 209a) sandwiched between adjacent stacked parts. The insulating layer of the liquid crystal display panel of Japanese Patent No. 3377447 is formed by applying an organic resin and spin-coating the resin to obtain an insulating layer of uniform thickness. However, the height difference in the routing wire region causes radial unevenness in the resulting resin film. If the height difference in the routing wire region increases, such a defect occurs with an increased probability, thereby resulting in reduction of manufacturing yield.